Chips are arranged in a grid pattern on a wafer since it is necessary to provide scrub lines between the chips.
According to a conventional chip arrangement determining method, a chip arrangement shown in FIG. 14A, where the center of the chips matches the center of the wafer, is compared with a chip arrangement shown in FIG. 14B, where two sides of a chip match the wafer coordinate axes having its origin at the center of the wafer. Then, the arrangement that can achieve a larger number of acquirable chips in a valid exposure area is adopted.
The larger the number of chips produced from one wafer, the more the manufacturing cost can be reduced. Therefore, it is important to maximize the number of acquirable chips in the valid exposure area. However, the conventional technique shown in FIGS. 14A and 14B cannot determine a chip arrangement that achieves rigorously the maximum number of chips. Furthermore, Japanese Patent Application Laid-Open No. 2000-195824 proposes a chip arrangement determining method that achieves virtually the maximum number of chips. According to the method proposed by Japanese Patent Application Laid-Open No. 2000195824, the relative position of the valid exposure area and chip arrangement that is neatly arranged in a grid pattern is shifted in each of the X and Y directions to search for a relative position that maximizes the number of acquirable chips.
However, according to this method, unless the pitch of one shift is made infinitely small, it is not always possible to obtain the relative position that maximizes the number of acquirable chips. In addition, this method raises a problem of an increased calculation time, as the pitch is made smaller. In other words, to obtain a strictly optimum chip arrangement, the required calculation time becomes extremely long.